KSA (anet0 anet1 anet2 anet3 anet4 anet5 anet6 anet7 anet8 anet9 anet10 anet11 anet12 anet13 anet14 anet15 anet16 anet17 anet18 anet19 anet20 anet21 anet22 anet23 anet24 anet25 anet26 anet27 anet28 anet29 anet30 anet31 bnet0 bnet1 bnet2 bnet3 bnet4 bnet5 bnet6 bnet7 bnet8 bnet9 bnet10 bnet11 bnet12 bnet13 bnet14 bnet15 bnet16 bnet17 bnet18 bnet19 bnet20 bnet21 bnet22 bnet23 bnet24 bnet25 bnet26 bnet27 bnet28 bnet29 bnet30 bnet31 snet0 snet1 snet2 snet3 snet4 snet5 snet6 snet7 snet8 snet9 snet10 snet11 snet12 snet13 snet14 snet15 snet16 snet17 snet18 snet19 snet20 snet21 snet22 snet23 snet24 snet25 snet26 snet27 snet28 snet29 snet30 snet31 vdd 0 vdd) ADDER

// Library name: PDVS
// Cell name: adder
// View name: schematic
subckt ADDER a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 VDD VSS PBULK

        WTriangle6_22 (c_22 g6_22 PBULK VDD VSS) WTriangle
		
		ends ADDER
		
               // Library name: PDVS
               // Cell name: WTriangle
               // View name: schematic
               subckt WTriangle C G PBULK VDD VSS
               MP0 (C G VDD PBULK) PFET w=(wdef*4) ld=ldef  \
                       
               MN0 (C G VSS VSS) NFET w=(wdef*2) l=ldef  
               ends WTriangle
               // End of subcircuit definition.
	   
